Roughly ten years ago the Qucs Development Team started the process of adding compact device modelling features to the widely used Qucs circuit simulator.
The purpose of this two part presentation is to provide the compact device modelling community with a detailed introduction to the history and capabilities of the modelling features implemented in the Qucs-S multi-simulator software package. The slides from this presentation are intended to be a reference source when developing Qucs-S compact device models.
The properties and use of these simulation modelling tools are introduced and their application described with a series of semiconductor device models.
This GPL software package provides users with an extensive range of simulation and modelling tools, including (1) Ngspice, SPICE OPUS and Xyce and (2) subcircuits, non-linear EDD, SPICE B style sources, Verilog-A modules, XSPICE Code Models, SPICE netlist synthesisers, Verilog-A, module and XSPICE Code Model synthesisers. 2017 the first stable version of the multi-simulator version of Qucs, called Qucs-S, was released. In the later stages of the presentation participants are also introduced to using the Berkeley MAPP tools with Qucs-S/Xyce. Throughout the talk a series of modelling case studies outline the stages in the development of Verilog-A models for established and SiC semiconductor devices. the presentation is based on the Qucs-S, QucsStudio and the MAPP/Octave FOSS software.
For this reason, in an attempt to encouraging all who attend to experiment with Verilog-A. Similarly, access to freely available Verilog-A modelling tools and circuit simulators is essential if Verilog-A modelling techniques are to be widely adopted. With the adoption of Verilog-A as the standardised model interchange language by CMC, a knowledge of this subject is of increasing importance to the modelling community. The purpose of this presentation is provide an overview of the fundamentals of the Verilog-A hardware description language and its use in compact modelling of established and emerging semiconductor technology devices. The performance of a number of Qucs-S modelling extensions are demonstrated with a GaN HEMT compact device model and data obtained from tests using the Qucs-S/Ngspice/Xyce © /SPICE OPUS multi-engine circuit simulator. The multi-simulator version of Qucs is a freely available tool that offers extended modelling and simulation features compared to those provided by legacy circuit simulators. Particular importance is placed on the interaction between Qucs-S schematics, Equation-Defined Devices, SPICE B behavioural sources and HDL scripts.
This paper introduces a number of new features recently implemented in the “Quite universal circuit simulator – SPICE variant” (Qucs-S), including structure and fundamental schematic capture algorithms, at the same time highlighting their use in behavioural semiconductor device modelling. Current trends in circuit simulation suggest a growing interest in open source software that allows access to more than one simulation engine while simultaneously supporting schematic drawing tools, behavioural, Verilog-A and XSPICE component modelling, and output data post-processing.